1. Field of the Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing a double gate oxide layer having a varying thickness.
2. Description of the Related Art
In recent years the manufacture of integrated circuits has improved dramatically while production costs have continued to decline. As a result, there has been tremendous growth in the development of electronic products that rely on the use of integrated circuits. However, individual devices are not able to adequately support the demands of many of the latest electronic technologies. Thus, the production of devices with a logic circuit and memory circuit on the same chip (System on Chip) SOC is becoming more common.
There are important considerations related to the integration of logic and memory devices on the same chip. With regard to the logic device, an important consideration is operating speed. When the logic device operates under low voltage conditions its transistor is smaller than that of the memory device and the gate oxide layer is thinner. On the other hand, reliability and stability are important considerations with regard to the memory device. The memory device usually operates under high voltage, the gate oxide layer of its transistor is thicker than the logic device.
Additionally, when conventional shallow trench isolation structures are formed, a chemical mechanical polishing process is used to remove silicon dioxide from the top of the active region, leaving silicon dioxide remaining in the trench structure. However, the silicon nitride layer that covers the active region is harder than the silicon dioxide layer. Thus, when a polishing step is performed to expose the silicon nitride layer, difficulties are encountered. As a consequence, dishing easily occurs in the shallow trench structures.
Hence, the conventional method of manufacture provides a double gate oxide layer that attempts to complement both operational speed and reliability and seeks to mitigate problems in the formation of shallow trench isolation structures.
As shown in FIG. 1A, a silicon nitride layer 102 is formed on a substrate 100. A plurality of trenches 104 is formed in the substrate 100 to define active areas (not shown) of the substrate 100. A silicon dioxide layer 106 is formed over the silicon nitride layer 102 to fill the trenches 104.
As shown in FIG. 1B, a photoresist layer 108 is formed over the silicon dioxide layer 106. Through a reverse tone mask procedure, part of the silicon dioxide layer 106, on top of a large area active areas is removed. A silicon dioxide layer 106a remains on the silicon nitride layer 102.
As shown in FIG. 1C, the photoresist layer 108 is removed. The silicon dioxide layer 106a is removed using a mechanical polishing procedure until the substrate 100 is exposed. A silicon dioxide layer 106b remaining from the silicon dioxide layer 106a forms isolation structures in the trenches 104.
A double gate oxide layer is then formed by the following steps. As shown in FIG. 1D, a first thermal oxidation process is performed on the substrate 100 to form an oxide layer 110 on the substrate 100.
As shown in 1E, a photoresist layer 112 is formed to cover a portion of the oxide layer 110. A lithographic etching procedure is conducted to remove oxide layer 110 from the area on the substrate 100 designated as a logic circuit region. The silicon oxide layer 110a covered by the photoresist layer 112 is not removed.
As shown in FIG. 1F, after the photoresist layer 112 has been removed, a second thermal oxidation process is performed on the entire substrate 100, a thin oxide layer 110b is formed on the substrate 100 designated as the logic circuit region to serve as a gate oxide layer.
The area on the substrate 100 designated as a memory circuit region includes oxide layers 110a and 110b. Together these two oxide layers 110a and 110b form the gate oxide for the memory circuit region. Based on the foregoing, the gate oxide layer of the memory circuit region is thicker than the gate oxide layer of the logic circuit region.
However, there are some problems occur in the above-stated method. Because the gate oxide layer on the active areas of the high-voltage device comprises two oxide layers 110a and 110b that are formed in different steps, interface exists between the two oxide layers 110a and 110b. This, in turn, weakens the endurance of the gate oxide layer for high voltage operation. Although an annealing process can be performed to mitigate this problem, annealing can not entirely reduce the presence of interface between the two oxide layers 110a and 110b. Consequently, the adverse affects cause by the presence of interface cannot be entirely eliminated.
Additionally, when the second thermal oxidation process for forming the oxide layer 110b is conducted, in the memory circuit region of high-voltage device, oxygen is diffused through the oxide layer 110a to react with silicon of the substrate, so as to form silicon dioxide. Thus, the second oxide layer 110b formed in the memory circuit region is thinner than the second oxide layer 110b formed in the logic circuit region. Even though the gate oxide layer, in the memory circuit region, including a oxide layers 110a and 110b is thicker than the second oxide layer 110b formed in the logic circuit region. However, the difference in thickness of the second oxide layer 110b across regions leads to difficulties in controlling the thickness of the gate oxide layer in the memory circuit region.
Furthermore, when the chemical mechanical process forming shallow trench isolation structures is conducted, a reverse tone mask is used to perform lithographic etching. Additionally, when a gate oxide layer having a varying thickness is formed, another lithographic etching procedure is conducted. The frequent use of mask and lithographic procedures in the process of manufacturing a semiconductor is an indication of the complexity of the conventional method of manufacture.
The invention provides a method of manufacturing a double gate oxide layer. A substrate has trenches that divide the substrate into a memory circuit region and a logic circuit region. A dielectric layer is formed on the substrate to fill the trenches. The dielectric layer of the logic region is removed, thereby exposing the substrate. An ion implantation step is performed on the substrate of the logic circuit region using a reverse tone mask. A conformal barrier layer is formed over the substrate. A spin-on layer is formed over the barrier layer. A chemical mechanical polishing step is performed to remove the spin-on layer, the barrier layer, and dielectric layer outside the trenches, thereby exposing the substrate. A thermal oxidation step is performed to form a double gate oxide layer that is thicker in the logic circuit region than it is in the memory circuit region.
The ion implantation step of the invention, creates differences in the speed of substrate oxidation within the logic circuit region and the memory circuit region. In the subsequent stage of manufacture, the thermal oxidation step simultaneously forms a double gate oxide layer having a varying thickness. Thus, concern that interface will form between the thicker gate layers is unnecessary. Moreover, the ion implantation step can be performed using the same reverse tone mask for forming shallow trench isolation structures, eliminating the need for the additional photoresist step. Thus, the method of this invention involves less complexity.
The conventional method of manufacturing a double gate oxide layer requires two thermal oxidation steps to complete. Moreover, during the lithographic etching process of forming the oxide layer, the alternating steps of thermal oxidation and lithographic etching may create pollutants, which affect the quality of the double gate oxide layer.
The method of creating the double gate oxide layer having a varying thickness does not require a mask for patterning the gate oxide layer. Reducing the number of photoresist and lithographic etching steps simplify the process of manufacture and enhances productivity.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.